Autonomous and Critical Embedded Systems

PhD defense Amine Naji

Amine Naji will defend his PhD thesis entitled « Timing Analysis for Time-Predictable Architectures » on Wednesday, June 12, at 10 AM in the lecture room Grenat of Télécom Paris.

The defense jury is comprised of :

  • Karine Heydemann, Associate Professor, UPMC (Paris 6)
  • Isabelle Puaut, Professor, University of Rennes I
  • Jens Knoop, Professor, Vienna University of Technology
  • Albert Cohen, Senior Research Scientist, ENS (supervisor)
  • Mathieu Jan, Engineer-Researcher, CEA List (co-supervisor)
  • Florian Brandner, Associate Professor, Télécom Paris (co-supervisor)

With the rising complexity of the underlying computer hardware, the analysis of the timing behavior of real-time software is becoming more and more complex and imprecise. Time-predictable computer architectures thus have been proposed to provide hardware support for timing analysis. The goal is to deliver tighter worst-case execution time (WCET) estimates while keeping the analysis overhead minimal.These estimates are typically provided by standalone WCET analysis tools.

The emergence of time-predictable architectures is, however, quite recent. While several designs have been introduced, efforts are still needed to assess their effectiveness in actually enhancing the worst-case performance. For many time-predictable hardware,timing analysis is either non-existing or lacking proper support. Consequently,time-predictable architectures are barely supported in existing WCET analysis tools. The general contribution of this thesis is to help filling this gap and turning some opportunities into concrete advantages. For this, we take interest in the Patmos processor. The already existing support around Patmos allows for an effective exploration of techniques to enhance the worst-case performance. This is delivered through the interplay between the hardware, the compiler, and the timing analysis.We thus not only provide some missing timing analysis support, but we also target hardware/software optimizations to enhance performance.

Main contributions include: (1) Handling of predicated execution in timing analysis,(2) Comparison of the precision of stack cache occupancy analyses, (3) Analysis of preemption costs for the stack cache, (4) Preemption mechanisms for the stack cache,and (5) Prefetching-like technique for the stack cache. In addition, we present our WCET analysis tool Odyssey, which implements timing analyses for the Patmos processor.

Commentaires Clos.